Parallel Data Switch

ABSTRACT

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

CROSS-REFERENCE TO RELATED PATENTS

The disclosed system and operating method are related to subject matterdisclosed in the following patents which are incorporated by referenceherein in their entirety: (1) U.S. Pat. No. 5,996,020 entitled, “AMultiple Level Minimum Logic Network”, naming Coke S. Reed as inventor;(2) U.S. Pat. No. 6,289,021 entitled, “A Scalable Low Latency Switch forUsage in an Interconnect Structure”, naming John Hesse as inventor; and(3) U.S. Pat. No. 6,754,207 entitled, “Multiple Path WormholeInterconnect”, naming John Hesse as inventor.

BACKGROUND

Components of large computing and communication systems can beconfigured with interconnect structures of switch chips connected byinterconnect lines. Increasing the switch-chip port count decreases thenumber of chip-to-chip hops, resulting in lower latency and lower cost.What is needed in these systems is switch chips that have high portcount and are also able to handle short packets.

SUMMARY

Embodiments of an interconnect apparatus enable improved signalintegrity, even at high clock rates, increased bandwidth, and lowerlatency. An interconnect apparatus can comprise a plurality of logicunits and a plurality of buses coupling the plurality of logic units ina selected configuration of logic units arranged in triplets comprisinglogic units LA, LC, and LD. The logic units LA and LC are positioned tosend data to the logic unit LD. The logic unit LC has priority over thelogic unit LA to send data to the logic unit LD. For a packet PKTdivided into subpackets, a subpacket of the packet PKT at the logic unitLA, and the packet specifying a target either: (A) the logic unit LCsends a subpacket of the packet PKT to the logic unit LD and the logicunit LA does not send a subpacket of the packet PKT to the logic unitLD; (B) the logic unit LC does not send a subpacket of data to the logicunit LD and the logic unit LA sends a subpacket of the packet PKT to thelogic unit LD; or (C) the logic unit LC does not send a subpacket ofdata to the logic unit LD and the logic unit LA does not send asubpacket of the packet PKT to the logic unit LD.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention relating to both structure and method ofoperation may best be understood by referring to the followingdescription and accompanying drawings:

FIG. 1 is a data structure diagram illustrating an embodiment of aformat of a packet comprising a number of sub-packet flits;

FIG. 2A is a schematic block diagram depicting a high-level view aswitch described in an embodiment of referenced U.S. Pat. Nos. 6,289,021and 6,754,207 including node arrays, connection lines, and FIFOs;

FIG. 2B is a schematic block diagram showing a high-level view of aswitch in an embodiment of the system disclosed herein comprising nodearrays interconnects;

FIG. 3A is a schematic block diagram illustrating a pair of simpleswitch nodes as described in referenced U.S. Pat. Nos. 6,289,021 and6,754,207;

FIG. 3B is a schematic block diagram showing a connected pair of nodesas described in the “flat latency” or “double-down” version of theswitches described in referenced U.S. Pat. Nos. 6,289,021 and 6,754,207;

FIG. 4 is a schematic block diagram depicting a building block for anode in an embodiment of the disclosed system (referred to herein as anLDM module) including a one-tick delay logic element, a one-tick delayFIFO element, and a multiplexing device for combining busses;

FIG. 5 is a block diagram showing four interconnected LDM modules inaccordance with an embodiment of the disclosed system;

FIG. 6 is a block diagram illustrating a switching node used in anembodiment of the disclosed system;

FIG. 7 is a block diagram showing the source and timing of the controlsignals sent to the logic elements in an embodiment of the switchingnode of the disclosed system;

FIG. 8 is a block diagram illustrating control registers used in thelogic elements of the switching nodes of an embodiment of the systemdisclosed herein;

FIGS. 9A, 9B, and 9C are schematic block diagrams that illustrateinterconnections of nodes on various levels of the interconnectstructure;

FIG. 10 is a timing diagram which illustrates timing of messagecommunication in the described interconnect structure; and

FIG. 11 is a pictorial representation illustrating the format of amessage packet including a header and payload.

DETAILED DESCRIPTION

The devices, systems, and methods disclosed herein describe a networkinterconnect system that is extremely effective in connecting a largenumber of objects, for example line cards in a router, network interfacecards in a parallel computer, or other communication systems anddevices. The described network interconnect system has extremely highbandwidth as well as extremely low latency.

Computing and communication systems attain highest performance whenconfigured with switch chips that have high port count and are also ableto handle short packets. The Data Vortex® switch chips described inincorporated U.S. Pat. Nos. 5,996,020 and 6,289,021 have extremely highport counts and have the ability to transmit short message packets.

The systems and methods disclosed herein include several improvementsover incorporated U.S. Pat. Nos. 6,289,021 and 6,754,207, attained byone or more of a number of enhancements, including the following twobasic improvements: 1) the bandwidth is increased and the first-bit-into last-bit-out latency is decreased by using parallel data linesbetween nodes; and 2) the bandwidth is further increased and the latencyis further reduced by a logic that sets up a data path through theswitch that contains a one-bit-long parallel FIFO at each level,enabling the use of a much faster clock than was possible inincorporated U.S. Pat. Nos. 6,289,021 and 6,754,207.

Incorporated U.S. Pat. No. 6,289,021 describes a switch that is suitableto be placed on a chip. In that system, data (in the form of packets)passes through the switch in wormhole fashion on one-bit wide datapaths. The packets include a header and a payload. The first bit of theheader is a status bit (set to a value of 1 in most embodiments)indicating the presence of a message. In a simple arrangement, theremaining header bits represent the binary address of a target outputport. The topology of the switch includes a richly connected set ofrings. A (2^(N)×2^(N)) switch includes rings arranged in (N+1) levelswith connections between rings on different levels. Packets enter theswitch at level N and exit the switch at level 0. The header of amessage packet entering the switch on level N has one status bit and Ntarget address bits. The logic at a node on level N makes routingdecisions based on: 1) the status bit; 2) the first bit of the addressin the header; 3) a control signal sent from a node on level N−1; and 4)(in the basic embodiment) a control signal from a node on level N. Thefirst bit of the address in the header is used by the logic on level N.When the logic on a level N node directs a packet to a node on levelN−1, the first bit of the address is discarded. This is done for severalreasons; 1) The first address bit is not needed for routing decisions onlower levels; 2) the discarding of this bit allows the message packetson level N−1 to travel ahead of the packets on level N so that, based onincoming packets, level N−1 nodes can send control signals to level Nnodes, thus enabling the level N−1 nodes to direct level N traffic: 3)the discarding of the first header bit ensures that the most significantbit of the remaining header bits is the bit that is needed to route thepacket on level N−1. This process continues throughout the switch sothat a packet on level K has one status bit followed by K address bits.

A consequence of this design is that data paths can be established thatcut directly between levels. The timing of the system is such that twoclock ticks are required for a status bit to move between two logicnodes on the same ring, but only one tick is required for the status bitto move between two nodes on different levels (a node on a level K ringis referred to as a level K node). Therefore, if the path of a packetthrough the switch contains N downward steps (steps between rings ondifferent levels) and J steps between two nodes on a ring at a givenlevel, then (N+2J+1) ticks are required before the first payload bitarrives at the output level 0. When the status bit is on level 0, thereare 2J one-tick delays on different levels, with one data bit in each ofthe one-bit FIFO delay elements. The passing of information throughmultiple transistors on nodes at different levels necessarily limits theclock rate of the system. In fact, if a packet passes down at each step,the status bit arrives at level 0 while the first payload bit is onlevel N, the top entry level.

In contrast, for the system described herein, each bit of the packetpasses through at least one single-tick FIFO on each level,advantageously enabling the signal to be reconstituted at each node andenabling the system described herein to operate at higher clock ratesthan systems described in incorporated U.S. Pat. No. 6,289,021.

The switching systems described in incorporated U.S. Pat. Nos.5,996,020, 6,289,021, and 6,754,207 provide low latency with highbandwidth and also support short packets. The topology of the switchesin incorporated U.S. Pat. Nos. 5,996,020, 6,289,021, and 6,754,207includes a richly interconnected set of rings. FIG. 2A is a high-levelblock diagram of an embodiment of a switch described in incorporatedU.S. Pat. Nos. 6,289,021 and 6,754,207. The entire structure illustratedin FIG. 2A fits on a single chip. The interconnection lines 210, 212,214, 216 and 218 are bit serial. The specification that a packet fits ona single ring calls for inclusion of FIFO elements 220. To decrease theprobability of a packet passing through FIFO 220, all of the packets areinserted into a single input node array through lines 202. The switchillustrated in FIG. 2A can be built using simple nodes illustrated inFIG. 3A or by using “double-down” or “flat latency” nodes illustrated inFIG. 3B.

First consider the simple switch U illustrated in FIG. 3k One aspect ofthe operation of the switches of U.S. Pat. Nos. 6,289,021 and 6,754,207is that the first bit of a data packet can enter the switch node U onlyat specific packet entry times. At a given packet entry time T, no morethan one packet can enter the switch node U. This is the case because ofthe novel use of control lines described in the incorporated U.S. Pat.Nos. 5,996,020, 6,289,021, and 6,754,207.

For each switch node U of FIG. 3A on level N-K, there is a K longpoly-bit PB_(U)=(b₀, b₁, b₂, . . . b_(K-1)) such that each packet PKentering U has a target destination whose binary representation hasleading bits (b₀, b₁, b₂, . . . b_(K-1)). Each packet that exits switchnode U through line 306 has a target destination whose binaryrepresentation has leading bits (b₀, b₁, b₂, . . . , b_(K-1), 1). Nextconsider the switch node L on level K such that each packet PK enteringL has a poly-bit PB_(L)=PB_(U) so that each packet PK entering L has atarget destination whose binary representation has leading bits (b₀, b₁,b₂, . . . , b_(K-1)). Each packet that exits switch node L through line316 has a target destination whose binary representation has leadingbits (b₀, b₁, b₂, . . . , b_(K-1), 0).

In case a packet PK enters U and the target address of PK has leadingbits (b₀, b₁, b₂, . . . , b_(K-1), 1) and the control line 310 indicatesa non-busy condition, then PK will exit U through line 306. Otherwise,PK must exit U through line 304. In case a packet PK enters L and thetarget address of PK has leading bits (b₀, b₁, b₂, . . . , b_(K-1), 0)and the control line 320 indicates a non-busy condition, then PK willexit L through line 316. Otherwise, PK must exit. L through line 314.

The “double-down” switch 380 illustrated in FIG. 3B combines nodes U andL using additional logic and interconnection lines 342 and 344. Thedouble-down switch DD 380 is positioned so that each packet that entersswitch DD on level N-K has a destination whose target address has Kleading bits PB_(DD)=(b₀, b₁, b₂, . . . , b_(K-1)). Switch DD ispositioned in the network so that each packet that exits node U of DDthrough line 326 has a target address with leading bits (b₀, b₁, b₂, . .. , b_(K-1), 1) and each packet that exits node L of DD through line 336has a target address with leading bits (b₀, b₁, b₂, . . . , b_(K-1), 0).

The switch DD operates as follows when a packet PKT enters node U:

-   -   1) If a packet PKT enters node U of DD through line 328 and the        leading address bits of the target of PKT are (b₀, b₁, b₂,        b_(K-1), 1), then a) if there is no busy signal on line 330,        then the logic of U directs the packet PKT down line 326: or b)        if there is a busy signal on line 330, then the logic of U        directs the packet PKT through line 324 to another double-down        switch in the network. In either case, the logic of U sends a        busy signal on line 344 to node L to indicate that line 326 is        busy.    -   2) If a packet PKT enters node U of DD through line 328 and the        leading address bits of the target of PKT are (b₀, b₁, b₂, . . .        , b_(K-1), 0), then a) if there is no busy signal on line 344,        then the logic of U directs the packet PKT through line 342 to        node L so that the logic of L can send PKT down line 336; or b)        if there is a busy signal on line 344, then the logic of U        directs the packet PKT through line 324 to another double-down        switch in the network. The logic of U sends a busy signal on        line 344 to node L to indicate that line 326 is busy only if        there is a busy signal on line 330.

Packets entering node L behave similarly. Thus, when a packet PKT entersnode L of the switch DD, the following set of events occur:

-   -   1) If a packet PKT enters node L of DD through line 338 and the        leading address bits of the target of PKT are (b₀, b₁, b₂, . . .        , b_(K-1), 0), then a) if there is no busy signal on line 348,        then the logic of L directs the packet PKT down line 336; or b)        if there is a busy signal on line 348, then the logic of L        directs the packet PKT through line 334 to another double-down        switch in the network. In either case, the logic of L sends a        busy signal on line 344 to node U to indicate that line 336 is        busy,    -   2) If a packet PKT enters node L of DD through line 338 and the        leading address bits of the target of PKT are (b₀, b₁, b₂, . . .        , b_(K-1), 1), then a) if there is no busy signal on line 344,        then the logic of L directs the packet PKT through line 342 to        node U so that the logic of U can send PKT down line 326; or b)        if there is a busy signal on line 344, then the logic of L        directs the packet PKT through line 334 to another double-down        switch in the network. The logic of L sends a busy signal on        line 344 to node U to indicate that line 336 is busy only if        there is a busy signal on line 348.

The switching system described in the system disclosed herein representsimportant improvements over the switching system described inincorporated U.S. Pat. Nos. 6,289,021 and 6,754,207. The mainimprovements include: 1) the addition of parallel data paths through thesystem that enable higher bandwidths than were possible in the systemsbuilt in the incorporated U.S. Pat. Nos. 6,289,021 and 6,754,207; 2) amodified timing system that simultaneously enables the creation of datapaths having FIFOs at each logic node with the advantages of said FIFOsincluding the ability to use high clock rates: 3) a timing system thatemploys only one tick for a packet flit to move between nodes ondifferent levels and two ticks for a packet flit to move between nodeson the same level. Advantageously, the FIFO lines 214 of FIG. 2A areeliminated.

FIG. 1 illustrates the layout of a packet. The packet is decomposed intoQ sub-packets referred to as flits. Each of the flits has R bits. Theflits are designed to travel through an R wide bus. The first flit, F₀102, is the header flit. It consists of a status bit H₀, N routing bitsH₁, H₂, . . . , H_(N), and additional bits (set to 0 in FIG. 1) that canbe used to carry other information, e.g. error correction bits or QOS.The status bit H₀ is set to 1 to indicate the presence of a packet. TheN routing bits represent the binary address of the target. Therefore, aswitch with N routing bits, is used in a switch of radix 2^(N). A logicL on level K uses bit. H_(K) in conjunction with control bits to routeF₀.

FIG. 2A represents a high level block diagram of the switch presented inincorporated U.S. Pat. Nos. 6,289,021 and 6,754,207. FIG. 2B representsa high level block diagram of the switch of the present patent whereinall header bits can be used to route the packet through the switch. Inreferenced U.S. Pat. Nos. 6,289,021 and 6,754,207 and also in thepresent disclosure, the node arrays are arranged in rows and columns.The node array NA(U,V) in a radix 2^(N) switch includes 2^(N) switchingnodes on level U in column V. In U.S. Pat. Nos. 6,289,021 and 6,754,207and also in the present system, in an example embodiment, a switch ofradix 2^(N) has (N+1) rows (or levels) of node arrays from an entrylevel N to an exit level 0. The switch has some number M of columns(where the number of columns is a design parameter). There are importantnovel improvements in the system introduced in the disclosed system. Inthe disclosed system, the lines between the node arrays include bussesthat replace the single-bit-wide lines used in patents no. 2 and no. 3.The nodes in the node array have novel new designs that enable lowerlatencies and higher bandwidths. Additionally, in incorporated U.S. Pat.Nos. 6,289,021 and 6,754,207, the system includes a FIFO shift register220 of sufficient length so that an entire packet can fit on a givenring on level 0; two packets can fit on a ring on level 1, and ingeneral 2^(R) packets can fit on a ring on level R. This FIFO can beeliminated in switches using the technology of the present disclosurebecause the width of the parallel bus will make it possible to have asufficient number of active nodes, thus enabling entire messages to fitin the active elements of a row of nodes. Referring to FIG. 2B, eachdata carrying line can include a bus with a width that is equal to thelength of an R-long sub-packet as illustrated in FIG. 1. The R longsub-packet can be referred to as a flit. The busses connect nodes inwhich each node is a module containing a one-tick logic element followedby a one tick delay element followed by a multiplexer (an LDM module).Two flits fit in an LDM module. Therefore, a packet containing Q flitscan fit in Q/2 LDM modules on a single row of node arrays in FIG. 2B. Inone illustrative embodiment, the top level (level N) contains LDMmodules on a single ring. The LDM modules on level N−1 are arranged ontwo rings. The bottom node array includes 2^(N) rings with each ringincluding M nodes connected by an R-wide bus. The arrangement of thenodes and busses in the node arrays make the ring structure possible.Each ring on level 0 must be long enough to hold an entire packetconsisting of Q flits. Each ring on level 0 delivers packets to a singletarget address. A plurality of output ports 238 can connect from asingle level 0 ring. Each of these outputs from a single ring deliversdata to the same target output. Data is input into the structure throughinput busses 222. In the simple embodiment, as shown, each logic node ona given level W is connected to forward packets to the next logic nodeon the associated ring and also is positioned to forward packets to oneof two logic nodes on level W−1. In the present configuration (asdepicted in U.S. Pat. Nos. 6,289,021 and 6,754,297) a logical element onlevel W−1 has priority over a logic node on level W to forward data to alogic element on level W−1. In the illustrative example presentedherein, each level contains the same number of logic nodes.

In embodiments of incorporated U.S. Pat. Nos. 6,289,021 and 6,754,207,ail of the packets enter node array NA(N,0) (where N denotes the levelof the array and 0 denotes the entry angle of the node array) in orderto minimize the probability of a given packet entering FIFO 220. Theelimination of the FIFO 220 enables the embodiments of the presentdisclosure to provide for the insertion of packets at a plurality ofangles. The plurality of insertion angles reduces the number of packetsinserted at any given angle, thereby reducing congestion. In the presentinvention, the first flit F₀ of a packet can enter a node only atspecified entry times that are different for different nodes in thesystem.

An embodiment of the presently-disclosed switch has connections thatcorrespond to the connections illustrated in FIG. 3B. Therefore, thewiring pattern topology for the disclosed system, as illustrated in FIG.2B, can be the same as the wiring pattern topology illustrated in FIG.2A and described in incorporated U.S. Pat. Nos. 5,996,020, 6,289,021,and 6,754,207.

Referring to FIG. 4, a block diagram of an individual switching module400 is shown including a logic element 402, a delay element 404 and amultiplexing element 406. The module with logic, delay and multiplexer(mux) is referred to as an LDM module. The LDM modules are componentsused in the construction of the switching nodes in the node arraysillustrated in FIG. 2B. Timing of the packet entry into a logic element402 is important for correct operation of the high-speed parallel switchof the disclosed system. Each logic device 402 is capable of holdingexactly one flit of a packet. Moreover, each delay device 404 is alsocapable of holding exactly one packet flit. At the conclusion of a timestep, the logic device 402 may or may not contain one flit of a packet.Similarly, at the conclusion of a time step, the delay device 404 alsomay or may not contain one flit of a packet. In case the delay devicecontains one flit F_(L) of a packet P and F_(L) is not the last flit ofthe packet (i.e., L<Q), then the logic device contains flit F_(L+1) ofthe packet. If L≠0 and F_(L) is in a logic unit or delay unit, then thelocation of flit F_(L) at time T_(S) is equal to the location of flitF_((L-1)) at time T_(S−1). In this manner, packets travel in wormholefashion through the switch.

In the illustrative embodiment, an LDM module comprises logic, delay,and multiplexer devices configured to synchronize timing of a packet.

Referring to FIG. 5 in conjunction with FIG. 4, basic operations andtiming of the LDM modules are described. The LDM module with logicelement L₁ is in the node array NA(W,Z); logic element L₂ is in NA(W,Z+1): L₃ is in NA(W−1, Z): and logic element L₄ is in NA(W−1,Z+1).

At each packet insertion time for L₁, the logic unit L, checks for aflit arrival by checking for a status bit H₀ set to 1. In case, at aflit arrival time T_(S) for logic unit L₁, the logic senses that H₀, isset to 0, the logic unit identifies that no packet is arriving in thistime slot and takes no action until the next first flit packet arrivaltime. If at a first flit arrival time T_(S) for L₁ (as identified by aclock or counter) the logic unit senses a 1 in the status bit slot H₀ inF₀, the logic unit ascertains that it contains the first flit of a validpacket PKT and precedes as follows:

-   -   (A) if 1) based on the bit H_(W) of F₀, L₁ determines if a path        exists from L₄ to a target output of PKT, and 2) the control        signal from L₃ indicates that L₁ is free to use line 412, then        L₁ sends the first flit F₀ of PKT through M₃ to arrive at L₄ at        time T_(S+1).    -   (B) If one or both of the above conditions 1) and 2) is not met,        then L₁ sends the first flit F₀ of PKT to D₁ in order to arrive        at D₁ at time T_(S+1) and subsequently to arrive at L₂ at time        T_(S+2) (one unit of time after first flits arrive at L₄).

A detailed discussion of the use of the routing bit H_(W) and thecontrol signals is included in the discussions of FIGS. 6, 7, and 8.Timing of first flit arrival at logic units on different levels in thesame column is important for the proper operation of the switchingsystem. Since first flits arrive at logic elements in NA(W−1,Z+1) onetime unit before first flits arrive at logic elements in NA(W,Z+1),sufficient time is available for control signals generated on level W−1to control the routing of packets on level W.

Given that an initial flit F₀ of a packet PKT arrives at a logic unit Lin time step T_(S), then the next flit F₁ of PKT will arrive at L intime step T_(S+1). This continues until the last flit F_(Q−1) of PKTarrives at the logic unit L at time T_(S+Q−1). Similarly, given thearrival of an initial flit F₀ of a packet PKT arrives at a delay unit Din time step T_(S)+₁, then the next flit F₁ of PKT will arrive at D intime step T_(S+2). This continues until the last flit F_(Q−1) of PKTarrives at D at time T_(S+Q). Each time that a flit of a packet arrivesat a logic or delay unit, the signal of the flit is regenerated. Thissignal regeneration at each tick allows for higher chip clock rates. Ina simple “single-down” embodiment, an LDM module can be used as a nodein the switch.

Referring to FIG. 6 a switching node used in the switch of an embodimentof disclosed system is shown. The switching node contains two LDMmodules 610 and 620 and a 2×2 crossbar 602. Suppose the switching noderepresented in FIG. 6 is in node array NA(W,Z). The LDM modules are oftwo types: 1) a type α LDM module 620 that is able to control thecrossbar 602 by sending a signal down line 608 and 2) a type β module610 that is not able to control the crossbar 602. Suppose theinteresting case where the level W is not equal to either 0 or N. Theset of packet entry times for the type α module 620 is equal to the setof packet entry times for the type β module 610.

Referring to FIG. 7, a schematic block diagram illustrates an embodimentof an interconnect apparatus which enables improved signal integrity,even at high clock rates, increased bandwidth, and lower latency. Theillustrative interconnect apparatus comprises a plurality of logic unitsand a plurality of buses coupling the plurality of logic units in aselected configuration of logic units which can be considered to bearranged in triplets comprising logic units LA 624, LC 724, and LD 710.The logic units LA 624 and LC 724 are positioned to send data to thelogic unit LD 710. The logic unit LC 724 has priority over the logicunit LA 624 to send data to the logic unit LD 710. For a packet. PKTdivided into subpackets, a subpacket of the packet PKT at the logic unitLA 624, and the packet specifying a target either: (A) the logic unit LC724 sends a subpacket of the packet PKT to the logic unit LD 710 and thelogic unit LA 624 does not send a subpacket of the packet PKT to thelogic unit. LD 710: (B) the logic unit LC 724 does not send a subpacketof data to the logic unit LD 710 and the logic unit LA 624 sends asubpacket of the packet PKT to the logic unit LD 710; or (C) the logicunit LC 724 does not send a subpacket of data to the logic unit. LD 710and the logic unit LA 624 does not send a subpacket of the packet PKT tothe logic unit LD 710.

In the illustrative interconnect structure, the logic, delay, andmultiplexer units can be configured with insufficient memory to hold theentire packet, and thus have only a bus-wide first-in-first-out (FIFO)buffer. Thus, packets are communicated on a bus wide data path.

A logic node does not reassemble a packet. A first subpacket, called aflit, of a packet PKT arrives at a logic node LA at a given time T₁. Attime T₂, the first flit of PKT arrives at the next downstream logic unitor delay unit. Also at time T₂, the second flit of PKT arrives at logicunit LA 624. In fact, the packet is never reassembled in the switch itleaves the switch one flit at a time. As a detail, a flit formed of Rbits (See FIG. 1) travels through the switch in wormhole fashion andexits through a SER-DES (serializer-deserializer) module connected to asequential interconnect that runs R times as fast.

Logic unit LA 624 will send PKT to logic unit LD 710 provided that 1) apath exists from logic unit LD 710 to the target output port for PKT;and 2) logic unit LA 624 is not blocked from traveling to logic unit LD710 by a logic element LC with a higher priority than logic unit LA 624to send to logic unit LD 710. Referring to FIG. 7, only logic unit LC724 has a higher priority than logic unit LA 624 to send to logic unitLD 710 whereas both logic units LB and LE have a higher priority thanlogic unit LA 624 to send to logic unit LF. In the example, a flit ofPKT is at logic unit LA 624. Logic unit LA 624 routes the first flit ofPKT based on header information and incoming control bits. Logic unit LA624 sends the second flit of PKT to the same element that it sent thefirst flit. In any case, logic unit LA 624 cannot hold onto a packet, ifa flit arrives at time T₁ it is forwarded at time T₂.

The interconnect structure transfers the packets and subpackets in asequence of time step. With a sequence of flits of the packet PKTentering the logic unit LA 624 at the operating time at an instant.Accordingly, the data communication operation can be considered tooperate at instances in time.

In the illustrative embodiment, a first flit, or subpacket, of thepacket PKT contains routing information through a switch to the target.

The logic unit LC 724 uses a control signal sent to the logic unit. LA624 to enforce priority over the logic unit LA 624 to send packets tologic unit LD 710.

A logic unit routes a packet based on packet header information and alsobased on control signals from other logic units.

The interconnect structure can further comprise a one-tickfirst-in-first-out (FIFO) buffer. A flit (subpacket) entering a logicunit passes through the one tick FIFO at the logic unit, regeneratingthe signal at each logic unit.

In some embodiments, the interconnect structure can operate so that, forthe logic unit LA 624 positioned to send packets to a plurality of logicunits including the logic unit LD 710, either Case 1 or Case 2 hold. InCase 1, the logic unit LA 624 determines that LD is the logic unit thatis most appropriate to receive packet PKT, and either the logic unit LC724 sends a packet to logic unit LD 710 and the logic unit LA 624 sendsthe PKT to a logic unit LG distinct from LD; or no logic unit withhigher priority than the logic unit LA 624 to send packets to the logicunit LD 710 sends a packet to the logic unit LD 710 and the logic unitLA 624 sends the packet PKT to the logic unit LD 710. In Case 2, thelogic unit. LA 624 determines that sending the packet PKT to the logicunit LD 710 is unacceptable, and the logic unit LA 624 sends the packetPKT in the logic unit LG distinct from the logic unit LD 710 or to thelogic unit LF 720 distinct from the logic unit LD 710.

For the logic unit LA 624 receiving a first subpacket of the packet PKTat a time T_(s), if the logic unit LA 624 sends the first subpacket ofthe packet. PKT to the logic unit LD 710, then logic unit LD 710receives the first subpacket of packet PKT at a time T_(S+1). If thelogic unit LA 624 sends the first subpacket of the packet PKT to thelogic unit LG, then the first subpacket passes through a delay unit DAand arrives at the logic unit LG at a time T_(S+2). If the logic unit LC724 sends a first subpacket of a packet QKT to the logic unit LD 710 andthe first subpacket of a packet QKT blocks packet PKT from traveling tothe logic unit LD 710, then the subpacket QKT arrives at the logic unitLD 710 at time T_(S+1).

In some embodiments, if the logic unit LA 624 determines that the logicunit LD 710 is a most appropriate logic unit to receive the packet PKT,then the logic unit LD 710 reaches that determination based on therouting information in the packet PKT. If the logic unit LA 624determines that sending the packet PKT to the logic unit LD 710 is notacceptable, then the logic unit LD 710 reaches the determination basedon the routing information in the packet. PKT.

Referring to FIG. 7 in conjunction with FIGS. 6 and 3B, data and controllines that govern the high-speed parallel data path switching node 600are described. Packets arrive at logical element LA on line 704 fromanother logic element on level W or on level W+1. At a given packetentry time T_(S) for logical element. LA, exactly one of the followingconditions is satisfied:

-   -   1) no first flit F₀ arrives at logic unit LA;    -   2) exactly one first flit arrives at logic unit LA from a logic        element on level W, but no first flit F₀ arrives at logic unit        LA from a logic element on level W+1; and    -   3) exactly one first flit arrives at logic unit LA from a node        on level W+1, but no first flit F₀ arrives at logic unit LA from        a node on level W.

Similarly, packets arrive at logic element LB from a logic element onlevel W+1 or from a logic element on level W. At logic node LB packetentry time T_(S), either no first flit arrives at logic element LB orexactly one first flit arrives at logic element LB. Importantly, giventhat a first flit F₀ of a packet PKT arrives at a logic element L_(A) attime T_(S), the next flit F₁ of PKT arrives at L_(A) at time T_(S+1),followed by the other flits of PKT so that the last flit F_(Q−1) of PKTarrives at L_(A) at time T_(S+Q−1). Similarly, given that flit F_(C)(with C<Q) of PKT is in delay element DEL at time T_(D) then flitF_(C+1) of PKT is in delay element DEL at time T_(D+1). Thus at eachlogical element and each delay element, the signal is reconstructed.This feature of the presently disclosed system, which is not shown inU.S. Pat. Nos. 6,289,021 and 6,754,207, enables the switch chip clock torun faster than the clock in the systems depicted in U.S. Pat. Nos.6,289,021 and 6,754,207.

With continued reference to FIG. 7 in conjunction with FIG. 6, the node600 is on level W of the N+1 level switch. Define Δ to be N−W.Corresponding to the node 600, a Δ long binary sequence BS (b₀, b₁, . .. , b_(Δ−1)) exists such that each packet entering logic unit LA orlogic unit LB of node 600 has a target address whose leading bits areBS. Each time that a packet PKT moves down a level in the switch, anadditional bit of the target address of PKT is set. Each packet enteringlogic element LD has a target whose binary address has leading bits (b₀,b₁, . . . , b_(Δ−1), 1). Each packet entering logic element LF has atarget whose binary address has leading bits (b₀, b₁, . . . , b_(Δ−1),0). The bus 622 connects LA and LB to a logic element LD 710 in a nodeon level W−1 so that a packet P with first flit F₀ in logic unit LA orlogic unit LB is able to progress to its target output through LDprovided that the bit H_(W) of F₀ is equal to 1 and other control lineconditions (discussed below) are satisfied. The bus 612 connects logicunit LA and logic unit LB to a logic element LF 720 in a node on levelW−1 so that a packet PKT with first flit F₀ in logic unit LA or logicunit. LB is able to progress to its target output through logic elementLF provided that the bit H_(W) of F₀ is equal to 0 and other controlline conditions (discussed below) are satisfied.

A logic element LC 724 exists in a LDM module 722 on level W−1 such thatthe logic element LC is positioned to send data to logic element. LD 710through delay unit DC. Also, a logic element LE 714 exists on level W−1such that the logic element LE 714 is able to send data to LF 720through delay unit DE. Suppose that T_(S) is a packet arrival time forlogic elements LA 624 and LB 614. Then T_(S+1) is a packet arrival timeat logic unit LF. A packet PKT traveling from logic element. LE to LFmust have its first flit F₀ in DE at time T_(S) and therefore must haveits first flit in LE at time T_(S−1). Similarly, a packet PKT travelingfrom LC to LD must have its first flit arrive in LC at time T_(S−1).Therefore, T_(S−1) is a packet arrival time for both logic elements LCand LE.

The lack of static buffers in the switch can be compensated for apriority scheme for competing messages to travel to logic element LD orLF. The priority scheme gives highest priority to level W−1 packets andgives the bar setting (where the packet travels horizontally on the samepath) of crossbar 602 priority over the cross setting (where the packettravels diagonally to an alternate path) of that switch. Therefore, thepriority scheme for the first flits F₀ of packets entering LD 710 attime T_(S+1) is as follows:

-   -   1) A packet whose first flit F₀ is in DC at time T_(S) has        priority one to travel to logic unit LD and such a packet will        always arrive at logic unit LD at time T_(S+1);    -   2) A packet whose first flit F₀ is in logic unit LA 624 at time        T_(S) and whose F₀ bit H_(W) is 1 has priority two and will        travel through switch 602 set to the bar state to arrive at        logic unit LD at time T_(S+1), provided there is no priority one        packet arriving at logic unit LD at time T_(S+1); and    -   3) A packet whose first flit F₀ is in logic unit LB 614 at time        T_(S) and whose F₀ bit H_(W) is 1 has priority three and will        travel through switch 602 set to the cross state to arrive at        logic unit LD at time T_(S+1), provided that no priority one or        priority two packet will arrive at logic unit LD at time        T_(S+1).

The priority scheme guarantees that lines 732 and 622 cannot possiblycarry information at the same time. Therefore, the signals from thosetwo lines can be joined in the multiplexer MC with no loss of fidelity.Notice that it is not necessary to designate a tick for multiplexer MC.A similar situation exists for multiplexer ME.

Similarly, the priority scheme for the first flits F₀ of packetsentering LF 720 at time T_(S+1) is as follows:

-   -   1) A packet whose first flit F₀ is in delay DE at time T_(S) has        priority one to travel to logic LF and such a packet will always        arrive at logic LF at time T_(S+1);    -   2) A packet whose first flit F₀ is in logic LB 614 at time T_(S)        and whose F₀ bit H_(W) is 0 has priority two and will travel        through switch 602 set to the bar state to arrive at logic LF at        time T_(S+1), provided there is no priority one packet arriving        at logic LF at time T_(S+1); and    -   3) A packet whose first flit F₀ is in logic LA 624 at time T_(S)        and whose F₀ bit H_(W) of F₀ is 0 has priority three and will        travel through switch 602 set to the cross state to arrive at        logic LF at time T_(S+1), provided that no priority one or two        packet will arrive at LF at time T_(S+1).

Refer to FIG. 6 in conjunction with FIG. 7 and FIG. 8. The integer Wdenotes the integer such that, in FIG. 7, the logical elements LA, LB,LG, and LH are on level W of the switch and the logical elements LC. LD,LE, and LF are on level W−1 of the switch. The priority scheme isenforced by logic unit control registers CR and CL which are set bycontrol packets from logic or delay units in the LDM modules. Each ofthe logic elements in the parallel double-down switch contains twocontrol registers CR (remote control) and CL (local control) and eachcontrol register contains two bits, thus allowing each register to storethe binary representation of any one of the integers 0, 1, 2, or 3.T_(S) is packet time arrival at the logical elements LA and LB: T_(S+1)is an arrival time at LD, and LF; is an arrival time at LG and LH. T_(S)is an arrival time at DC and DE and T_(S−1) is an arrival time at LC andLE. Prior to time T_(S−1,) the registers C_(R) and C_(L) in LA and LBare set to 0. The register CR in LA is set to a value distinct from 0 bya control signal on line 728 from LC. The register CR in LB is set to avalue distinct from 0 by a control signal on line 718 from LE. Theregister CL in LB is set to a value distinct from 0 by a control signalon line 604 from LA. The register CL in LA is set to a value distinctfrom 0 by a control signal on line 606 from LB. The LDM module 620 isable to set the crossbar switch 602 to the bar or cross state by sendinga signal from LA down line 608. The crossbar controlling LDM module 620is referred to as the type a LDM module. The LDM module 610 has no meansto control the crossbar 602 and is referred to as the type β LDM module.The crossbar has three states: state 0 indicates that the crossbar isnot ready to receive data; state 1 indicates that the crossbar is in thebar state and is ready to receive data: state 2 indicates that thecrossbar is in the cross state and is ready to receive data. If a packetflit arrives at the crossbar while the crossbar is in state 0, the flitwill be stored in a flit wide buffer until the crossbar state is set to1 or 2. There is a logic that keeps track when the last flit of a packetexits the crossbar. The state of the crossbar remains constant whileflits of a given packet are passing through it. When the last flit exitsthe crossbar, the crossbar is placed in state 0.

In an illustrative embodiment, functionality of the control registers inlogical element LA can be defined as follows:

-   -   1) CR=1 implies logical element LD is blocked by a packet from        logical element LC;    -   2) CR=2 implies logical element LD is not blocked and can        receive a packet from logical element LA;    -   3) CL=1 implies logical element LB is sending a packet to        logical element LF though the crossbar in the bar state;    -   4) CL=2 implies logical element LF is not blocked and can        receive a packet from logical element LA: and    -   5) CL=3 implies logical element LF is blocked by a packet from        logical element. LE.

In an illustrative embodiment, functionality of the control registers inlogical element LB can be defined as follows:

-   -   1) CR=1 implies logical element LF is blocked by a packet from        logical element LE;    -   2) CR=2 implies logical element LF is not blocked and can        receive a packet from logical element LB;    -   3) CL=1 implies logical element LA is sending a packet to        logical element LD through the crossbar in the bar state;    -   4) CL=2 implies logical element LD is not blocked and can        receive a packet from logical element LB; and    -   5) CL=3 implies logical element LD is blocked by a packet from        logical element LC.

The switch illustrated in FIG. 6, FIG. 7, and FIG. 8 can operate asfollows:

In a first action, at or before packet arrival time T_(S), the CRregisters are set by a signal on line 728 from logical element LC and bya signal on line 718 from logical element LE.

In a second action, at packet arrival time T_(S), the logical unit LAproceeds as follows:

-   -   1) Case 1: The first flit of a packet PKT_(A) arrives at logical        element LA on line 704; the header bit H_(W) of PKT_(A) is set        to one indicating that logical element LD is on a path to the        target output of PKT_(A); and the logical element LA register        CR=2 indicating that logical element LD will not receive a        packet from logical element LC at time T_(S+1). In this case,        logical element. LA sends a signal down line 608 to set the        crossbar to the bar state. Then logical element LA sends the        first flit of packet PKT_(A) through the crossbar to arrive at        logical element LD at time T_(S+1). Then logical element LA        sends a signal through line 604 to set the CL register of        logical element LB to 1.    -   2) Case 2: The conditions of Case 1 do not occur and the CR        register of logical element LA is set to 2 indicating that        logical element LC is not sending a packet to arrive at logical        element LD at time T_(S+1). In this case, logical element LA        sends a signal trough line 604 to set the CL register of logical        element LB to 2.    -   3) Case 3: The conditions of Case 1 do not occur and the CR        register of logical element LA is set to one indicating that        logical element LC is sending a packet to arrive at logical        element LD at time T_(S+1). In this case, logical element LA        sends a signal trough line 604 to set the CL register of logical        element LB to 3.

In a third action, at packet arrival time T_(S), the logical unit LBproceeds as follows:

-   -   1) Case 1: The first flit of a packet PKT_(B) arrives at logical        element LB on line 702; the header bit H_(W) of PKT_(B) is set        to zero and the logical element LB register CR=2 indicating that        logical element LF will not receive a packet from logical        element LE at time T_(S+1). In this case, logical element LB        sends a first flit of PKT_(B) to the crossbar to travel through        the crossbar after the crossbar has been set to the bar state so        as to arrive at logical element LF at time T_(S+1). Then logical        element LB sends a control signal through line 604 to set the CL        register of logical element LA to 1.    -   2) Case 2: The conditions of Case 1 do not occur and the CR        register in logical element LB is set to 2 indicating that        logical element LE is not sending a packet to arrive at logical        element LF at time T_(S+1). In this case, logical element LB        sends a signal through line 606 to set the CL register of        logical element LA to 2.    -   3) Case 3: The conditions of Case 1 do not occur and the CR        register in logical element LB is set to 3 indicating that        logical element LE is sending a packet to arrive at logical        element LF at time T_(S+1). In this case, logical element LB        sends a signal through line 606 to set the CL register of        logical element LA to 3.

In a fourth action, if logical element LA has already set the crossbarto the bar state, then logical element LA takes no further action. Iflogical element LA has not set the crossbar to the bar state, thenlogical element LA examines its CL register after the CL register hasbeen set to a non-zero value. If the CL register contains a 1, thenlogical element LA sets the crossbar to the bar state. If the CLregister contains a number distinct from 1, then logical element LA setsthe crossbar to the cross state.

In a fifth action, at this point the logic at logical element LA hasinformation of the state of the crossbar and logical element LA proceedsas follows:

-   -   1) Case 1: There is no packet flit in logical element LA at time        T_(S), implying that no further action is required of logical        element LA.    -   2) Case 2: The first flit of a packet PKT_(A), arrived at        logical element LA at time T_(S). The crossbar is in the bar        state, the first flit of a packet PKT_(A) was sent through the        crossbar as described hereinabove implying that no further        action is required of logical element LA.    -   3) Case 3: The first flit of a packet PKT_(A) arrived at logical        element LA at time T_(S). The crossbar is in the bar state, the        first flit of a packet PKT_(A) was not sent through the crossbar        in the second action as described hereinabove implies that the        first flit of packet PKT_(A) is to be sent to delay unit DA.        Therefore, logical element LA sends the first flit of PKT_(A) to        delay unit DA.    -   4) Case 4: The first flit of a packet PKT_(A) arrived at logical        element. LA at time T_(S). The crossbar is in the cross state,        the header bit H_(W) of PKT_(A) is set to 0, and the register CL        of logical element. LA is set to 2 then the first flit of        PKT_(A) will be sent through the crossbar to arrive at logical        element LF at time T_(S+1).    -   5) Case 5: The first flit of a packet PKT_(A) arrived at logical        element LA at time T_(S). The crossbar is in the cross state,        but the conditions of case 4 do not occur. Then the first flit        of PKT_(A) will be sent to delay unit DA.

In a sixth action, which can be performed simultaneously with fifthaction, if either the CL register of logical element LB is set to 1, orLB sets the CL register of logical element LA to 1, then the logic atlogical element LA has information that the crossbar is set to the barstate. If neither of these conditions is met, then logical element LA isaware that the crossbar is set to the cross state. Logical element LBproceeds as follows:

-   -   1) Case 1: No packet flit is in logical element LB at time        T_(S), implying that no further action is required of logical        element LB.    -   2) Case 2: The first flit of a packet PKT_(S) arrived at logical        element LB at time T_(S). The crossbar is in the bar state, the        first flit of a packet PKT_(B) was sent through the crossbar as        described hereinabove, implying that no further action is        required of logical element LB.    -   3) Case 3: The first flit of a packet PKT_(B) arrived at logical        element LB at time T_(S). The crossbar is in the bar state, the        first flit of a packet PKT_(B) was not sent through the crossbar        in the second action as described hereinabove, implying that the        first flit of packet PKT_(B) is to be sent to delay unit DB.    -   4) Case 4: The first flit of a packet PKT_(S) arrived at logical        element LB at time T_(S). The crossbar is in the cross state,        the header bit H_(W) of PKT_(B) is set to 1, and the register CL        of logical element. LB is set to 2 then the first flit of        PKT_(S) will be sent through the crossbar to arrive at logical        element LD at time T_(S+1).    -   5) Case 5: The first flit of a packet PKT_(B) arrived at logical        element LB at time T_(B). The crossbar is in the cross state,        but the conditions of case 4 do not occur. The first flit of        PKT_(A) will be sent to delay unit DB.

In the illustrative example, the priority is given to the bar state overthe cross state. In another example priority can be given to the crossstate. In still another example priority can be given to logical elementLA over logical element LB or to logical element LB over logical elementLA.

The multiplexer elements Improve structure compactness and performanceby reducing the amount of interconnection paths between nodes. In adifferent embodiment, the multiplexers may be omitted. Referring to FIG.7, notice that MC 738 and interconnect line 734 can be eliminated byconnecting interconnect line 732 to a first input of logic unit LD andconnecting interconnect line 622 to a second input of logic unit LD. Inanother simplified embodiment, a single LDM module can serve as a nodeof a switch. In this case, the crossbar in the node switching node canbe omitted. In another more complex embodiment, a switching node caninclude a number on LDM modules and a switch where the number N of LDMmodules is not equal to one or two and the switch is of radix N.

The structures and systems disclosed herein include significantimprovements over the systems described in the referenced U.S. Pat. No.5,996,020, 6,289,021, and 6,754,207, including one or more of thefollowing advantageous properties: 1) improved signal integrity even athigh clock rates, 2) increased bandwidth, and 3) lower latency.

Improvements include one or more of: 1) a bus-wide data path; 2) allheader bits sufficient to route data through the switch are contained inflit F₀; and 3) the signal is cleaned up at each logic unit and eachdelay unit of an LDM module.

FIGS. 9A, 9B and 9C are schematic block diagrams that showinterconnections of nodes on various levels of the interconnectstructure. FIG. 9A shows a node A_(RJ) 920 on a ring R of outermostlevel J and the interconnections of node A_(RJ) 920 to node B_(RJ) 922,device C 924, node D_(RJ) 926, node E_(R)(J−1) 928, node F_(R)(J−1) 930and device G 932. FIG. 9B shows a node A_(RT) 940 on a ring R of a levelJ and the interconnections of node A_(RT) 940 to node B_(RT) 942, nodeC_(R)(T+1) 944, node D_(RT) 946, node E_(R)(T−1) 948, node F_(R)(T−1)950 and node G_(R)(T+1) 952. FIG. 9C shows a node A_(R0) 960 on a ring Rof innermost level 0 and the interconnections of node A_(R0) 960 to nodeB_(R0) 962, node C_(R1) 964, node D_(R0) 966, device E 968 and nodeG_(R1) 972.

FIGS. 9A, 9B and 9C show topology of an interconnect structure. Tofacilitate understanding, the structure can be considered a collectionof concentric cylinders in three dimensions r, ⊖ and z. Each node ordevice has a location designated (r, ⊖, z) which relates to a position(r, 2π ⊖/K, z) in three-dimensional cylindrical coordinates where radiusr is an integer which specifies the cylinder number from 0 to J, angle θis an integer which specifies the spacing of nodes around the circularcross-section of a cylinder from 0 to K−1, and height z is a binaryinteger which specifies distance along the z-axis from 0 to 2^(J−1).Height z is expressed as a binary number because the interconnectionbetween nodes in the z-dimension is most easily described as amanipulation of binary digits. Accordingly, an interconnect structurecan be defined with respect to two design parameters J and K.

In FIGS. 9A, 9B and 9C interconnections are shown with solid lines witharrows indicating the direction of message data flow and dashed lineswith arrows indicating the direction of control message flow. Insummary, for nodes A, B and D and nodes or devices C, E, F, G:

-   -   1) A is on level t=r;    -   2) B and C send data to A;    -   3) D and E receive data from A;    -   4) F sends a control signal to A;    -   5) G receives a control signal from A;    -   6) B and D are on level T;    -   7) B is the immediate predecessor of A;    -   8) D is the immediate successor to A; and    -   9) C, E, F and G are not on level T.

Positions in three-dimensional cylindrical notation of the various nodesand devices is as follows:

-   -   1) A is positioned at node N(r, ⊖, z);    -   2) B is positioned at node N(r, ⊖−1, H_(T) (z));    -   3) C is either positioned at node N(r+1, ⊖−1, z) or is outside        the interconnect structure;    -   4) D is positioned at node N(r, ⊖+1, h_(T) (z));    -   5) E is either positioned at node N(r−1, ⊖+1, z) or is outside        the interconnect structure and the same as device F;    -   6) F is either positioned at node N(r−1, ⊖, H_(T−1) (z)) or is        outside the interconnect structure and the same as device E;    -   7) G is either positioned at node N(r+1, ⊖, h_(T) (z)) or is        outside the interconnect structure.

Note that the terms ⊖+1 and ⊖−1 refer to addition and subtraction,respectively, modulus K.

In this notation, (⊖−1)mod K is equal K when ⊖ is equal to 0 and equalto ⊖−1 otherwise. The conversion of z to H_(r) (z) on a level r isdescribed for z=[z_(J−1), . . . , z_(J−2), . . . , z_(r), z_(r−1), . . ., z₂, z₁, z₀] by reversing the order of low-order z bits from z_(r−1) toz₀] into the form z=[z_(J−1), z_(J−2), . . . , z_(r), z₀, z₁, z₂, . . ., z_(r−1)], subtracting one (modulus 2^(r)) and reversing back thelow-order z bits. Similarly, (⊖+1)mod K is equal 0 when ⊖ is equal toK−1 and equal to ⊖+1 otherwise. The conversion of z to hr (z) on a levelr is described for z=[z_(J−1), z_(J−)2, . . . , z_(r), z_(r−1), . . . ,z₂, z₁, z₀] by reversing the order of low-order z bits from Z_(r−1) toz₀] into the form z=[z_(J−1), z_(J−2), . . . , z_(r), z₀, z₁, z₂, . . ., z_(r−1)], adding one (modulus 2^(r)) and reversing back the low-orderz bits.

In accordance with one embodiment of the system depicted in FIGS. 9A, 9Band 9C, the interconnect structure can include a plurality of nodesarranged in a structure comprising a hierarchy of levels from a sourcelevel to a destination level; plurality of nodes spanning across-section of a level: a plurality of nodes in a cross-section span.The level of a node can be determined entirely by the position of thenode in the structure; and a plurality of interconnect lines couplingthe nodes in the structure. For a node N on a level L: (1) a pluralityof message input interconnect lines are coupled to a node on a previouslevel L+1; (2) a plurality of message input interconnect lines arecoupled to a node on the level L; (3) a plurality of message outputinterconnect lines are coupled to a node on the level L; (4) a pluralityof message output interconnect lines are coupled to a node on asubsequent level L−1; (5) a control input interconnect line is coupledto the message output interconnect line of a node on the level L−1; and(6) a switch is coupled to receive a message on the control inputinterconnect line and, in accordance with the message, to selectivelytransmit a message without buffering on the plurality of message outputinterconnect lines coupled to the subsequent level L−1 node or on theplurality of message output interconnect lines coupled to the level L.

In accordance with another embodiment of the system depicted in FIGS.9A, 9B and 9C, the interconnect structure can include a plurality ofnodes and a plurality of interconnect lines coupling the nodes. A node Xof the plurality of nodes can include a plurality of message inputinterconnect lines coupled to a node A distinct from the node X; and aplurality of message input interconnect lines coupled to a node Bdistinct from the node A and the node X. The node X accepts a messageinput from the node A and a message input from the node B with a controlsignal communicating between the node A and the node B for determining apriority relationship between conflicting messages. The control signalcan enforce the priority relationship between the sending of a messagefrom the node A to the node X and the sending of a message from the nodeB to the node X.

In accordance with a further embodiment of the system depicted in FIGS.9A, 9B and 9C, the interconnect structure can include a plurality ofnodes and a plurality of interconnect lines in an interconnect structureselectively coupling the nodes in a hierarchical multiple levelstructure. The hierarchical multiple level structure can be arranged toinclude a plurality of J+1 levels in an hierarchy of levels arrangedfrom a lowest destination level L₀ to a highest level L_(j) which isfarthest from the lowest destination level L₀. The level of a node canbe determined entirely by the position of the node in the structure withthe interconnect structure transmitting a message M in a plurality ofdiscrete time steps. A message M moving in a time step and theinterconnect structure having interconnections to move the message M inone of three ways in the time step including: (1) the message M enters anode in the interconnect structure from a device external to theinterconnect structure; (2) the message M exits the interconnectstructure to a designated output buffer; and (3) the message M eithermoves from a node U on a level L_(k) to a different node V on the samelevel L_(k) or moves from the node U to a node W on a level L_(i) wherek is greater than i so that the level L_(i) is closer to the destinationlevel L₀ than the level L_(k).

In accordance with other embodiments of the system depicted in FIGS. 9A,9B and 9C, the interconnect structure can include a plurality of nodes;and a plurality of interconnect lines selectively coupling the nodes ina hierarchical multiple level structure with the level of a node beingdetermined entirely by the position of the node in the structure inwhich data moves only unilaterally from a source level to a destinationlevel or laterally along a level of the multiple level structure. Datamessages can be transmitted through the multiple level structure from asource node to a designated destination node. A level of the multiplelevels can include one or more groups of nodes. The data message can betransmitted to a group of the one or more groups of nodes that is enroute to the destination node. A group of the one or more groups caninclude a plurality of nodes. The data message can be transmitted to anode N of the plurality of nodes of a group unilaterally toward thedestination level if the node is not blocked and otherwise the datamessage being transmitted laterally if the node is blocked.

In accordance with further embodiments of the system depicted in FIGS.9A, 9B and 9C, the interconnect structure can include a plurality ofnodes and a plurality of interconnect lines L interconnectingcommunication devices at the plurality of nodes. The nodes can includecommunication devices that communicate messages in a sequence ofdiscrete time steps including receiving messages and sending messages. Anode N of the plurality of nodes can include: (1) a connection to aplurality of interconnect lines LUN for transmitting a message from adevice U to the node N; (2) a connection to a plurality of interconnectlines LVN for transmitting a message from a device V to the node N; and(3) the network which has a precedence relationship PN(U,V) relating tothe node N and the devices U and V such that the device U has precedenceover the device V in sending a message to the node N so that for amessage MU at the device U that is directed to the node N via theplurality of interconnect lines LUN at a time step t and a message MV atthe device V that is directed to the node N via the plurality ofinterconnect lines LVN also at a time step t. The message MU issuccessfully sent to the node N and the node V uses a control signal todecide where to send the message MV.

In accordance with still further embodiments of the system depicted inFIGS. 9A, 9B and 9C, the interconnect structure can include a pluralityof nodes N and a plurality of interconnect lines L connecting theplurality of nodes N in a predetermined pattern. The interconnect linescarry messages M and control signals C. The messages M and controlsignals C can be received by a node of the plurality of nodes at adiscrete time step t and the messages M can be moved to subsequent nodesof the plurality of nodes in an immediately subsequent discrete timestep t+1. The plurality of interconnect lines L connecting the pluralityof nodes N can include: (1) a node NA having a message inputinterconnection for receiving a message MA, (2) a control inputinterconnection for receiving a control signal CA, (3) a direct messageoutput interconnection to a node ND, (4) a direct message outputinterconnection to a node NE, (5) a direct control outputinterconnection to a device G. A control logic for determining whetherthe message MA is sent to the node ND or the node NE can based on: (1)the control signal CA; (2) a location of the node NA within theplurality of interconnect lines L; and (3) a routing informationcontained in the message MA.

In still another embodiment, the interconnect structure can comprise aplurality of nodes N and a plurality of interconnect lines L connectingthe plurality of nodes N in a predetermined pattern. The plurality ofinterconnect lines L connecting the plurality of nodes N can include anode NA having a direct message input interconnection for receiving amessage MA and having a plurality of direct message outputinterconnections for transmitting the message MA to a plurality of nodesincluding a selected node NP being most desired for receiving themessage MA. The selected node NP can be determined only by routinginformation in a header of the message MA and the position of the nodeNA within the plurality of interconnect lines L. The selected node NPhas a plurality of direct message input interconnections for receiving amessage MP from a plurality of nodes including a priority node NB whichhas priority for sending a message to the selected node NP. The prioritynode NB can be determined by position of the node NB within theplurality of interconnect lines L so that: (1) if the node NA is thesame as the node NB, then the message MA is the message MP and is sentfrom the node NA to the node NP; and (2) if the node NA is not the sameas the node NB and the node NB directs a message MB to the node NP, thenthe message MB is sent from the node NB to the node NP.

In additional embodiments, the interconnect structure can comprise anetwork capable of carrying a plurality of messages M concurrentlycomprising a plurality of output ports P; a plurality of nodes N, theindividual nodes N including a plurality of direct message inputinterconnections and a plurality of direct message outputinterconnections; and a plurality of interconnect lines. The individualnodes N pass messages M to predetermined output ports of the pluralityof output ports P. The predetermined output ports P are designated bythe messages M. The plurality of interconnect lines can be configured inan interconnect structure selectively coupling the nodes in ahierarchical multiple level structure arranged to include a plurality ofJ+1 levels in an hierarchy of levels arranged from a lowest destinationlevel L0 to a highest level LJ which is farthest from the lowestdestination level L0, the output ports P being connected to nodes at thelowest destination level L0. The level of a node can be determinedentirely by the position of the node in the structure. The network caninclude a node NA of the plurality of nodes N, a control signaloperating to limit the number of messages that are allowed to be sent tothe node NA to eliminate contention for the predetermined output portsof the node NA so that the messages M are sent through the directmessage output connections of the node NA to nodes NH that are a level Lno higher than the level of the node NA, the nodes NH being on a path tothe designated predetermined output ports P of the messages M.

In accordance with an embodiment of the system depicted in FIGS. 9A, 9Band 9C, the interconnect structure can include a plurality of nodes anda plurality of interconnect lines in an interconnect structureselectively coupling the nodes in a hierarchical multiple levelstructure. The multiple level structure can be arranged to include aplurality of J+1 levels with J an integer greater than 0 in an hierarchyof levels arranged from a lowest destination level L0 to a highest levelLJ with the level of a node being determined entirely by the position ofthe node in the structure, the interconnect structure transmitting aplurality of multiple-bit messages entering the interconnect structureunsorted through a plurality of input ports. An individual message M ofthe plurality of messages can be self-routing. The individual message Mmoves in a plurality of ways including three ways which are sufficientfor the message M to exit the interconnect structure through an outputport designated by the message M. The three ways are: (1) the message Menters a node in the interconnect structure from a device external tothe interconnect structure, the message M designating one or moredesignated output ports; (2) the message M moves through a node in theinterconnect structure without buffering to a designated output port;and (3) the message M moves either through a node U on a level Lk of theinterconnect structure without buffering to a different node V on thesame level Lk or moves through the node U on a level Lk of theinterconnect structure without buffering to a node W on a level Linearer in the hierarchy to the destination level L0 than the level Lk.

In accordance with still other embodiments of the system depicted inFIGS. 9A, 9B and 9C, the interconnect structure can include a pluralityof nodes and a plurality of interconnect lines in an interconnectstructure selectively coupling the nodes in a structure. Theinterconnect structure transmits a plurality of multiple-bit messagesentering the interconnect structure unsorted through a plurality ofinput ports. An individual message M of the plurality of messages can beself-routing. The interconnect structure can include: (1) a node NEhaving a first data input interconnection from a node NA and a seconddata input interconnection from a node NF distinct from the node NA; and(2) a control interconnection between the node NA and node NF forcarrying a control signal to resolve contention for sending messages tothe node NE. The control signal can be supplied from the node NA or thenode NF each distinct from the node NE with which messages arecommunicated.

In accordance with further other embodiments of the system depicted inFIGS. 9A, 9B and 9C, the interconnect structure can include a pluralityof nodes and a plurality of interconnect lines in an interconnectstructure selectively coupling the nodes in a hierarchical multiplelevel structure. The multiple level structure can be arranged to includea plurality of J+1 levels with J an integer greater than 0 in anhierarchy of levels arranged from a lowest destination level L₀ to ahighest level L_(J). The interconnect structure receives a plurality ofmultiple bit messages unsorted through a plurality of input ports andtransmitting the multiple bit messages. An individual message M of theplurality of messages can be self-routing and moves through nodes usingwormhole routing in which only a portion of the multiple-bits of amessage are in transit between two nodes. The multiple-bit messageextends among multiple nodes. An individual message M moves in aplurality of ways including four ways which are sufficient for themessage M to exit the interconnect structure through an output portdesignated by the message M. The four ways are: (1) the message M entersa node in the interconnect structure from a device external to theinterconnect structure, the message M designating one or more designatedoutput ports; (2) the message M moves through a node in the interconnectstructure without buffering to a designated output port; (3) the messageM moves through a node on a level L_(k) of the interconnect structurewithout buffering to a different node on the same level L_(k); and (4)the message M moves through a node on a level Lk of the interconnectstructure without buffering to a node on a level L_(i) nearer in thehierarchy to the destination level L₀ than the level L_(k).

In accordance with further other embodiments of the system depicted inFIGS. 9A, 9B and 9C, the interconnect structure can include a pluralityof nodes and a plurality of interconnect lines in an interconnectstructure selectively coupling the nodes in a structure. Theinterconnect structure receives a plurality of multiple bit messagesunsorted through a plurality of input ports and transmits the multiplebit messages. An individual message M of the plurality of messages canbe self-routing and move through nodes using wormhole routing in whichonly a portion of the multiple bits of a message are in transit betweentwo nodes with the multiple-bit message extending among multiple nodes.The interconnect structure can include a node N_(E) that has a firstdata input interconnection from a node N_(A) and a second data inputinterconnection from a node N_(F): and a control interconnection betweenthe node N_(A) and node N_(F) that resolves contention for sendingmessages to the node N_(E).

In accordance with further other embodiments of the system depicted inFIGS. 9A, 9B and 9C, the interconnect structure can include a pluralityof nodes with each node having a plurality of input ports and aplurality of output ports, a logic associated with the plurality ofnodes, and a node X included in the plurality of nodes and having anoutput port opx. The node X can have a set of input terminals IPXwherein a logic associated with the node X can send messages entering aninput terminal of the set IPX to the output port opx. The logicassociated with the node X can be operational wherein if a message M_(P)arrives at an input port p of input port set IPX and a path exists fromthe output port opx to a target of message M_(P), then one of themessages arriving at input port set IPX will be sent to output port opxso long as the output port opx is not blocked by a message that is nottraveling through the node X.

In still further embodiments, the interconnect structure can comprise aplurality of interconnected nodes including distinct nodes F_(W), F_(B),and F_(X); means for sending a plurality of messages through theplurality of nodes including sending a set of messages S_(W) through thenode F_(W); and means for sending information i concerning routing ofthe messages in the message set S_(W) through the node F_(W) includingrouting a portion of the messages in the message set S_(W) through thenode F_(W) to the node F_(X). The interconnect structure can furthercomprise means associated with the node F_(B) for using the informationI to route messages through the node F₈.

In other embodiments, the interconnect structure can comprise aplurality of nodes including a node K a node set T, and a node set Sincluding nodes Y and Z; a plurality of interconnect paths connectingthe nodes; a plurality of output ports coupled to the plurality ofnodes; and logic that controls flow of data through the nodes to theoutput ports. The logic controls data flow such that: (1) the node X iscapable of sending data to any node in the set S; (2) the node set Tincludes nodes that can alternatively pass data that are otherwisecontrolled by the logic to flow through the node X; (3) any output portthat can access data passing through the node X can also access datapassing through the node Y; (4) the plurality of output ports include anoutput port O that can access data passing through the node X but cannotaccess data passing through the node Z; and (5) the logic controls flowof data through the node X to maximize the number of data messages thatare sent through a node in the set T such that the number of outputports accessible from the node in the set T is less than the number ofoutput ports that are accessible from the node X.

Referring to FIG. 10, a timing diagram illustrates timing of messagecommunication in the described interconnect structure. In variousembodiments of the interconnect structure, control of messagecommunication is determined by timing of message arrival at a node. Amessage packet, such as a packet 1100 shown in FIG. 11, includes aheader 1110 and a payload 1120. The header 1110 includes a series ofbits 1112 designating the target ring in a binary form. When a sourcedevice CU(⊖₁,z₁) at an angle. ⊖₁ and height z₁ sends a message packet Mto a destination device CU(⊖₂,z₂) at an angle. ⊖₂ and height z₂, thebits 1112 of header 1110 are set to the binary representation of heightz₂.

A global clock servicing an entire interconnect structure keeps integraltime modulus K where, again, K designates the number of nodes n at acylinder height z. There are two constants α and β such that theduration of α exceeds the duration of β and the following fiveconditions are met. First, the amount of time for a message M to exit anode N(T,⊖+1,h_(T)(z)) on level T after exiting a node N(T,⊖,z) also onlevel T is a. Second, the amount of time for a message M to exit a nodeN(T−1,⊖+1,z) on level T−1 after exiting a node N(T,⊖,z) on level T isα−β. Third, the amount of time for a message to travel from a device CUto a node N(r,⊖.z) is α−β. Fourth, when a message M moves from a nodeN(r,⊖,z) to a node N(r,⊖+1,h_(r)(z)) in time duration a, the message Malso causes a control code to be sent from node N(r,⊖,z) to a nodeN(r+1,⊖,h_(r)(z)) to deflect messages on the outer level r+1. The timethat elapses from the time that message M enters node N(r,⊖,z) until thecontrol bit arrives at node N(r+1,⊖,h_(r+1)(z)) is time duration β. Theaforementioned fourth condition also is applicable when a message Mmoves from a node N(J,⊖,z) to a node N(J,⊖+1,h_(J)(z)) at the outermostlevel J so that the message M also causes a control code to be sent fromnode N(J,⊖,z) to the device D outside of the network such that D sendsdata to N(J, ⊖+1,h_(j)(z)). In one embodiment, D=CU(⊖+1, h_(j)(z)). Thetime that elapses from the time that message M enters node N(r,⊖,z)until the control bit arrives at device CU(⊖,z) is time duration β.Fifth, the global clock generates timing pulses at a rate of α.

When the source device CU(⊖₁,z₁) sends a message packet M to thedestination device CU(⊖₂,z₂), the message packet M is sent from a dataoutput terminal of device CU(⊖₁,z₁) to a data input terminal of nodeN(J,⊖₁,z₁) at the outermost level J. Message packets and control bitsenter nodes N(T,⊖,z) on a level T at times having the form nα+Lβ where nis a positive integer. The message M from device CU(⊖₁,z₁) is sent tothe data input terminal of node N(J,⊖₁,z₁) at a time t₀−β and isinserted into the data input terminal of node N(J,⊖₁,z₁) at time to solong as the node N(J,⊖₁,z₁) is not blocked by a control bit resultingfrom a message traversing on the level J. Time t₀ has the form (⊖₂−⊖₁)α+Jβ. Similarly, there is a time of the form (⊖₂−⊖₁) α+Jβ at which adata input terminal of node N(J,⊖₁,z₁) is receptive to a message packetfrom device CU(⊖₁,z₁).

Nodes N(T,⊖,z) include logic that controls routing of messages based onthe target address of a message packet M and timing signals from othernodes. A first logic switch (not shown) of node N(T,⊖,z) determineswhether the message packet M is to proceed to a node N(T−1, ⊖+1,z) onthe next level T−1 or whether the node N(T−1, ⊖+1,z) is blocked. Thefirst logic switch of node N(T,⊖,z) is set according to whether asingle-bit blocking control code sent from node N(T−1,⊖,H_(T−1)(z))arrives at node N(T,⊖,z) at a time t₀. For example, in some embodimentsthe first logic switch takes a logic 1 value when a node N(T−1,⊖+1,z) isblocked and a logic 0 value otherwise. A second logic switch (not shown)of node N(T,⊖,z) determines whether the message packet M is to proceedto a node N(T−1,⊖+1,z) on the next level T−1 or whether the nodeN(T−1,⊖+1 z) is not in a suitable path for accessing the destinationdevice CU(⊖₂,z₂) of the header of the message packet M. The header ofthe message packet M includes the binary representation of destinationheight z₂(z₂(J), z₂(J−1), . . . z₂(T), . . . , z₂(1), z₂(0). The nodeN(T,⊖,z) on level T includes a single-bit designation z_(T) of theheight designation z (z_(J), z_(J−1), . . . , z_(T), . . . , z₁, z₀). Inthis embodiment, when the first logic switch has a logic 0 value and thebit designation z₂(T) of the designation height is equal to the heightdesignation z_(T), then the message packet M proceeds to the next levelat node N(T−1,⊖+1,z) and the destination height bit z₂(T) is strippedfrom the header of message packet M. Otherwise, the message packet Mtraverses on the same level T to node N(T,⊖+1,h_(T)(z)). If messagepacket M proceeds to node N(T−1,⊖+1,z), then message packet M arrives ata time t₀+(α−β) which is equal to a time (z₂−z₁+1) α+(J−1)β. If messagepacket M traverses to node N(T,⊖+1,h_(T)(z)), then message packet Marrives at a time t₀+α, which is equal to a time (z₂−z₁+1) α+Jβ. Asmessage packet. M is sent from node N(r,⊖,z) to node N(T,⊖+1,h_(T)(z)),a single-bit control code is sent to node N(T+1,⊖,h_(T)(z)) (or deviceCU(⊖,z) which arrives at time t₀+β. This timing scheme is continuedthroughout the interconnect structure, maintaining synchrony as messagepackets are advanced and deflected.

The message packet M reaches level zero at the designated destinationheight z₂. Furthermore, the message packet M reaches the targeteddestination device CU(⊖₂,z₂) at a time zero modulus K (the number ofnodes at a height z). If the targeted destination device CU(⊖₂,z₂) isready to accept the message packet M, an input port is activated at timezero modulus K to accept the packet. Advantageously, all routing controloperations are achieved by comparing two bits, without ever comparingtwo multiple-bit values. Further advantageously, at the exit point ofthe interconnect structure as message packets proceed from the nodes tothe devices, there is no comparison logic, if a device is prepared toaccept a message, the message enters the device via a clock-controlledgate.

Referring to FIGS. 10 and 11, an embodiment of the interconnectstructure can comprise a plurality of nodes arranged in a topology ofthree dimensions and means for transmitting a message from a node N to atarget destination. The means for transmitting a message from a node Nto a target destination can comprise means for determining whether anode en route to the target destination in the second and thirddimensions and advancing one level toward the destination level of thefirst dimension is blocked by another message; and means for advancingthe message one level toward the destination level of the firstdimension when the en route node is not blocked, and means for movingthe message in the second and third dimensions along a constant level inthe first dimension otherwise. The means for transmitting a message froma node N to a target destination can further comprise means forspecifying the first dimension to describe a plurality of levels, thesecond dimension to describe a plurality of nodes spanning across-section of a level, and the third dimension to describe aplurality of nodes in the cross-section of a level; means for sending acontrol signal from a node on the level of the en route node to the nodeN in the first dimension, the control signal specifying whether the nodeen route is blocked; means for timing transmission of a message using aglobal clock specifying timing intervals to keep integral time modulusthe number of nodes in a cross-section of a level; and means for settinga first time interval α for moving the message in the second and thirddimensions. The means for transmitting a message from a node N to atarget destination can still further comprise means for setting a secondtime interval α−β for advancing the message one level toward thedestination level, the global clock specifying a global time intervalequal to the second time interval, the first time interval being smallerthan the global time interval; and means for setting a third timeinterval for sending the control signal from the node on the level ofthe en route node to the node N, the third time interval being equal toβ.

Terms “substantially”, “essentially”, or “approximately”, that may beused herein, relate to an industry-accepted variability to thecorresponding term. Such an industry-accepted variability ranges fromless than one percent to twenty percent and corresponds to, but is notlimited to, materials, shapes, sizes, functionality, values, processvariations, and the like. The term “coupled”, as may be used herein,includes direct coupling and indirect coupling via another component orelement where, for indirect coupling, the intervening component orelement does not modify the operation. Inferred coupling, for examplewhere one element is coupled to another element by inference, includesdirect and indirect coupling between two elements in the same manner as“coupled”.

The illustrative pictorial diagrams depict structures and processactions in a manufacturing process. Although the particular examplesillustrate specific structures and process acts, many alternativeimplementations are possible and commonly made by simple design choice.Manufacturing actions may be executed in different order from thespecific description herein, based on considerations of function,purpose, conformance to standard, legacy structure, and the like.

While the present disclosure describes various embodiments, theseembodiments are to be understood as illustrative and do not limit theclaim scope. Many variations, modifications, additions and improvementsof the described embodiments are possible. For example, those havingordinary skill in the art will readily implement the steps necessary toprovide the structures and methods disclosed herein, and will understandthat the process parameters, materials, shapes, and dimensions are givenby way of example only. The parameters, materials, and dimensions can bevaried to achieve the desired structure as well as modifications, whichare within the scope of the claims. Variations and modifications of theembodiments disclosed herein may also be made while remaining within thescope of the following claims.

1.-19. (canceled)
 20. An apparatus, comprising: switching circuitry thatincludes a first logic element, a second logic element, a third logicelement, and one or more fourth logic elements, wherein the first logicelement is coupled to route first packet data to the second logicelement or the third logic element, wherein target information for thefirst packet data indicates the third logic element as a desired nexttarget for the first packet data, and wherein the first packet dataincludes multiple bits transmitted in parallel; wherein the first logicelement is configured to forward the first packet data to the thirdlogic element based on determining that the one or more fourth logicelements are not routing packet data to the third logic element; andwherein the first logic element is configured to forward the firstpacket data to the second logic element based on control signaling fromthe one or more fourth logic elements indicating that at least one ofthe one or more fourth logic elements is routing second packet data tothe third logic element.
 21. The apparatus of claim 20, wherein theswitching circuitry is configured to route data such that, subsequent tothe first logic element forwarding first packet data to the second logicelement, the second logic element is configured to receive controlsignaling from one or more fifth logic elements that do not receive thesecond packet data, such that the second packet data cannot block thefirst packet data from being forwarded to a desired sixth logic elementindicated as a desired next target for the first packet data by thetarget information.
 22. The apparatus of claim 20, wherein the switchingcircuitry includes multiple logical levels and wherein packet dataenters at one or more of the logical levels and propagates via one ormore of the levels to leave at one or more lower logical levels; whereinthe first and second logic elements are in a first level; and whereinthe third and fourth logic elements are in a second, lower level. 23.The apparatus of claim 22, wherein each of the multiple logic levels isconfigured to forward packet data to either a logic element on the samelogical level or a logic element on a next-lowest logical level based ontarget information and control information.
 24. The apparatus of claim23, wherein the first logic element is never blocked from forwardingpacket data to another logic element on the same logical level.
 25. Theapparatus of claim 20, where the first packet data is a multi-bitportion of a first packet received by the switching circuitry, whereinthe multi-bit portion has a first number of bits, and wherein theswitching circuitry is configured to route packet data using data bussesconfigured to transmit the first number of bits in parallel.
 26. Theapparatus of claim 20, wherein the first logic element is included in anode element that includes the first logic element a delay logicelement, and multiplexing circuitry, wherein the delay logic element andmultiplexing circuitry are configured to route data from the first logicelement to the second logic element to synchronize timing of packetdata.
 27. The apparatus of claim 20, wherein the apparatus is configuredto transmit an entire address sub-packet included in the first packetdata to each of multiple logic elements in the switching circuitrywithout discarding bits of the address sub-packet.
 28. The apparatus ofclaim 20, wherein the first packet data is a sub-packet of a packet thatincludes multiple sub-packets.
 29. A method, comprising: a first logicelement in a switch network receiving first packet data and determiningthat a third logic element is a desired next target for the first packetdata based on target information for the first packet data, wherein thefirst packet data includes multiple bits transmitted in parallel; thefirst logic element transmitting the first packet data to a second logicelement and not the third logic element based on control informationindicating that at least one of one or more fourth logic elements istargeting the third logic element; the first logic element receivingsecond packet data and determining that the third logic element is adesired next target for the second packet data based on targetinformation for the second packet data; and the first logic elementtransmitting the second packet data to the third logic element based oncontrol information indicating that the one or more fourth logicelements do not target the third logic element.
 30. The method of claim29, further comprising: the switch network routing the first packet dataaccording to a permutation such that, subsequent to the first logicelement forwarding packet data to the second logic element, the secondlogic element receives control signaling from one or more fifth logicelements that do not receive the second packet data, such that thesecond packet data does block the first packet data from being forwardedto a desired sixth logic element indicated as a desired next target forthe first packet data by the target information.
 31. The method of claim29, wherein the switching circuitry includes multiple logical levels andwherein packet data enters at one or more of the logical levels andpropagates via one or more of the levels to leave at one or more lowerlogical levels; wherein the first and second logic elements are in afirst level; and wherein the third and fourth logic elements are in asecond, lower level.
 32. The method of claim 29, wherein ones of themultiple logic levels forward packet data to either a logic element onthe same logical level or a logic element on a next-lowest logicallevel.
 33. The method of claim 29, further comprising delaying the firstpacket data for a tick between the first logic element and the secondlogic element.
 34. An apparatus, comprising: multiple logical levels ofswitch circuitry, wherein packet data enters at one or more of thelogical levels and propagates via one or more of the levels to leave atone or more lower logical levels, including: a first logic elementconfigured to determine whether to forward first packet data to a secondlogic element that is on the same level as the first logic element or toa third logic element that is on a lower level than the first logicelement, based on control signaling from one or more fourth logicelements that are on the lower level, wherein the first packet dataincludes multiple bits transmitted in parallel; wherein the one or morefourth logic elements are configured to provide a blocking controlsignal to the first logic element based on at least one of the one ormore fourth logic elements forwarding second packet data to the thirdlogic element, and wherein the first logic element is configured toforward the first packet data to the second logic element in response tothe blocking control signal.
 35. The apparatus of claim 34, wherein theapparatus is configured to route data packets such that, subsequent tothe first logic element forwarding packet data to the second logicelement in response to the blocking control signal, the second logicelement is configured to receive control signaling from one or morefifth logic elements in the lower level that do not receive the secondpacket data, such that the second packet data cannot block the firstpacket data from being forwarded to the lower level by the second logicelement.
 36. The apparatus of claim 34, wherein the level of the firstlogic element is arranged in a ring structure such that if the firstpacket data is blocked at each logic element on the level, it willreturn to the first logic element.
 37. The apparatus of claim 34,wherein each of the multiple logic levels is configured to forwardpacket data to either a logic element on the same logical level or alogic element on a next-lowest logical level.
 38. The apparatus of claim34, wherein the first packet data is a sub-packet of a packet thatincludes multiple sub-packets.
 39. The apparatus of claim 34, whereinthe first packet data is a multi-bit portion of a first packet receivedby the switching circuitry, wherein the multi-bit portion has a firstnumber of bits, and wherein the switching circuitry is configured toroute packet data using data busses configured to transmit the firstnumber of bits in parallel.
 40. The apparatus of claim 34, wherein thefirst logic element is included in a node element that includes thefirst logic element a delay logic element, and multiplexing circuitry,wherein the delay logic element and multiplexing circuitry areconfigured to route data from the first logic element to the secondlogic element to synchronize timing of packet data.
 41. The apparatus ofclaim 34, wherein the level of the first logic element includes aplurality of logic elements configured to forward packet data to thelower level, if not blocked by one or more other logic elements.
 42. Anapparatus comprising: switching circuitry that includes a first logicelement, a second logic element, a third logic element, and one or morefourth logic elements, wherein the first logic element is coupled toroute a first packet to the second logical element or the third logicelement and wherein target information for the first packet indicatesthat the third logic element as a desired next target for the firstpacket; wherein the one or more fourth logic elements are configured toa control signal that indicates whether or not the first logic elementis blocked from sending the first packet to the third logic element;wherein the first logic element is configured to, in response todetermining that that it is not blocked, forward the first packet to thethird logic element; and wherein the first logic element is configuredto, in response to determining that it is blocked based on the controlsignal, forward the first packet to the second logic element.
 43. Theapparatus of claim 42, wherein the one or more fourth logic elements areconfigured to block the first logic element, using the control signal,when sending a packet to the third logic element.
 44. The apparatus ofclaim 42, wherein the first packet is subdivided into a number ofsub-packets, wherein the first logic element and the one or more fourthlogic elements are configured to forward a sub-packet at a time, andwherein each sub-packet in the first packet is sent via the same paththrough logic elements of the switching circuitry based on routing ofthe first sub-packet in the first packet.
 45. The apparatus of claim 42,wherein the second logic element is configured to receive blockingcontrol information, from one or more fifth logic elements that indicatewhether it is blocked from forwarding data to a sixth logic element,wherein packet data is routed in the switching circuitry such that apacket that blocks the first packet from being forwarded from the firstlogic element to the third logic element cannot block the second logicelement from forwarding data to the sixth logic element.